1. Field
Embodiments relate to buried channel array transistor (BCAT) devices and methods of forming BCAT devices. More particularly, embodiments relate to a BCAT memory device that protects a cell bit line from shoulder attacks, has improved short margins, and/or has reduced loading capacitance relative to conventional devices.
2. Description of the Related Art
As semiconductor devices are becoming more and more integrated, device characteristics may suffer. For example, threshold voltages of devices, e.g., transistors, may be lowered. Refresh characteristics may also be degraded as channel lengths of transistors are shortened. Buried channels may be employed to help alleviate, e.g., such problems. More particularly, in a memory device, e.g., dynamic random access memory (DRAM) including BCATs, a loading capacitance of the bit lines may be relatively high, a short margin of a storage node may be relatively small, etc. Thus, devices having improved characteristics are desired.